The Reed-Solomon Code (hereinafter, RS code) is mainly used for recording media and external coding of digital transmissions, from the appropriateness in relation to the quality of the encoding efficiency and the error burst.
For example, the error correction code that is used with a compact disc is called the CIRC correction code (cross interleaved Reed-Solomon code); this is a product code that is combined with the interleave method. RS (28, 24) code is used as the external code, and RS (32, 28) code as the internal code, and they are called the C2 code and the C1 code, respectively. In either code, the RS encoding unit is constructed of 1 byte, and a single RS decoding block contains a parity check string of 4 bytes.
Generally, the RS code is a check string of 2t nits, and correction of t units is possible. In the correction of t units, it is necessary to know the t units of error positions, and the value of t units of error corresponding to the respective errors. The RS coding obtains an independent linear formula for 2t units by performing a syndrome calculation at the decoding side in relation to the generation of t units of error. By solving this formula, the error position for the above-mentioned t units, which is an unknown number of 2t units, and the value of the error of the above-mentioned t units corresponding to the respective error positions, can be found.
On the other hand, as for adopting a construction of a product code like the CIRC code, by applying a erasure flag to the RS-encoded block for which correction could not be done at the internal RS decoding in relation to the internal code and the RS-encoded block in which the possibility of error correction is comparatively high, erasure error correction becomes possible in the external RS decoding corresponding to the external code. The erasure units for the internal code to which the erasure flags were applied are dispersed in multiple external RS-encoded blocks by means of deinterleaving. In the erasure error correction, by assuming that there is an error present in the above-mentioned erasure unit, the simultaneous formulas that are obtained from the syndrome calculations are solved. Since the error positions are already known, the value of the error for the maximum 2t can be solved. In other words, it is possible to error-correct a maximum 2t units by executing the erasure error correction for the RS codes having check strings of 2t units.
The method for the erasure error correction is explained by offering an example of the CIRC code.
In the case of the CIRC code, by applying a erasure flag in the RS decoding (C1 decoding) for the C1 code, which is the internal code, the erasure error correction is possible in the RS decoding (C2 decoding) for the C2 code, which is the external code. Because t=2 in both the C1 code and the C2 code, in C1 coding, correction of a maximum 2 bytes is possible, but in the erasure error correction of C2 decoding, the correction of a maximum of 4 bytes is possible. The syndrome s.sub.0 to s.sub.3 and the error value e.sub.1 to e.sub.4 in that C2 code can be found as follows.
The code-generating polynomial expression Ge(x) for the CIRC code is shown by Formula 1 below. ##EQU1##
Here, .alpha. is the primitive element for the Galois field. At this time, s.sub.0 to s.sub.3 obtained by means of the syndrome calculations from the input string have the relationship shown by the following Formula 2 between the above-mentioned x.sub.1 to x.sub.4, and e.sub.1 to e.sub.4. ##EQU2##
Here, the symbol ".multidot." shows multiplication over the Galois field, and the symbol "+" shows addition over the Galois field. Below, as for the four basic mathematical operations between the elements of a given Galois field, it has been decided to show the calculations for that Galois field.
If the error values e.sub.1 to e.sub.4, which are unknown numbers, are found by solving the simultaneous formulas, the above-mentioned Formula 2 becomes as follows.
First, e.sub.4 is obtained as Formula 3 below. ##EQU3##
A simultaneous formula is reconstructed by substituting this e.sub.4 obtained in the above-mentioned Formula 2. In other words, as for the Galois field that was used in the CIRC code, by correcting it as in Formula 4 below, noting the fact that the addition and the subtraction are the same, the simultaneous formula of the above-mentioned Formula 2 is transformed to Formula 5 below. ##EQU4##
As for this, the solving of the simultaneous formula is a method that is frequently used when finding the sequence in manual calculations. If e.sub.3 is found by solving the simultaneous formula of Formula 5, it becomes like Formula 6 below. ##EQU5##
By executing the corrections in the same manner, the simultaneous Formula of the above-mentioned Formula 5 is modified as in Formulas 7 and 8 below. ##EQU6##
Also, if e.sub.2 is found by solving the simultaneous formula of Formula 8, it becomes Formula 9 below. ##EQU7##
Next, Formula 10 below is obtained by substituting this e.sub.2 that was found in the above-mentioned Formula 8.
[Mathematical Formula 10] EQU e1.rarw.s0+e2
In this manner, the error values e.sub.1 to e.sub.4 can be found sequentially.
In the above-mentioned method, in order to distinguish between those which were originally held as information, and the calculation operations that were conducted at the time of the actual decoding, the symbols "=" and "6" are used in different ways. In other words, the Formulas corresponding to the actual decoding calculations are Formulas 3, 4, 6, 7, 9, and 10, and in the Galois field, at least 23 additions, 17 multiplications, and 3 divisions are necessary.
On the other hand, in the event the erasure error correction is not conducted, corrections (double error corrections) can be done for a maximum of 2 bytes in the C2 decoding. At this time, the error values e.sub.1, e.sub.2, and the error positions X'.sub.1, X'.sub.2 are found from the syndromes s.sub.0 to s.sub.3.
Above, the quadruple erasure error correction, in other words, the number of erasure positions, is the decoding calculation processes for 4 cases.
A flow chart for the erasure error correction process according to the method used in the past is shown in FIG. 2.
As is shown in FIG. 2, the syndromes s.sub.0 to s.sub.3 are totaled from the receive string (step S1), and the erasure positions x.sub.1 to x.sub.4 are obtained from its erasure flag (step S2). Then, the number of the lead flags is counted, and this count value is set to n (step S3).
Next, in the case of n=4(2t) (step S4), the decoding calculations for the quadruple erasure error corrections are conducted according to the algorithms of the above-mentioned Formulas 3, 4, 6, 7, 9, and 10, and the error values e.sub.1 to e.sub.4 are found (step S5). Then, the correction operation is conducted by using the error values e.sub.1 to e.sub.4 and the erasure positions x.sub.1 to X.sub.4 (step S6).
Also, in the case of n=3(t&lt;n&lt;2t) (step S7), the decoding calculations for the triple erasure error corrections are conducted according to the algorithms of the above-mentioned Formulas 6, 7, 9, and 10, and the error values e.sub.1 to e.sub.4 are found (step S8). Then, the correction operation is conducted by using the error values e.sub.1 to e.sub.3 and the erasure positions x.sub.1 to x.sub.3 (step S6).
On the other hand, in the case of n.ltoreq.2 (T), the prescribed error corrections corresponding to this are executed (step S9, S6).
As was mentioned above, in the case of a quadruple erasure error correction, all of the syndromes s.sub.0 to s.sub.3 were used, but in the triple erasure error correction used in the past, only s.sub.0 to s.sub.2 were used. Also, the correction method in the case of n.ltoreq.2 (=t) was not clear. Lastly, in the method used in the past, there was the problem that the countermeasures for the case when an erroneous correction was generated were not sufficiently executed.
Below, an explanation is given in regard to the general construction of the Reed-Solomon decoding device that conducts the erasure error correction process presented above.
FIG. 3 is a construction diagram of the Reed-Solomon decoding device used in the past.
As is shown in FIG. 3, the Reed-Solomon decoding device 1 is equipped with the memory block 2, the bus I/F block 3, and the decoding calculations processing section 4.
The memory block 2 is equipped with the cache memories 5, 6, and the switches 7, 8.
The switch 7 selectively outputs the input data to the cache memories 5, 6. The switch 8 selectively outputs the storage content of the cache memory 5 to the corrections operation implementer 12.
The bus I/F block 3 is equipped with the input parameter calculator 9, the register B.sub.OUT 10, the binary counter 11, the corrections operations implementer 2, and the register B.sub.IN 13.
The decoding calculations processing section 4 is equipped with the switch 14, the register G.sub.IN 15, the register G.sub.OUT 16, and the decoding calculator 17.
FIG. 4 shows the time sequence for the data and the construction elements during the operation of the Reed-Solomon decoding device 1, (A) shows the input data, (B) the output data, (C) the storage condition of the register B.sub.OUT 10, (D) the storage condition of the register B.sub.IN 13, (E) the storage condition of the register G.sub.OUT 16, (F) the storage condition of the register G.sub.IN 15, and (G) the processing condition of the decoding calculator 17, respectively.
As is shown in FIG. 4, when the input/output is conducted for the input data related to the C1 code in the cache memory 5 to the memory block 2, as for the bus I/F block 3, the calculations are conducted for the decoding calculation input parameters by the input parameter calculator 9 for the input data related to the C1 code, and the correction operations are conducted by the correction operations implementer 12. Also, at this time, the C2 code processing is being conducted in regard to the input data related to the C2 code in the decoding calculations processing section 4.
Also, when the input/output is conducted for the input data related to the C2 code in the cache memory 6, as for the bus I/F block 3, the calculations are conducted for the decoding calculations input parameters by the input parameter calculator 9 for the input data related to the C2 code, and the correction operations are conducted by the correction operations implementer 12. Also, at this time, in the decoding calculations processing section 4, the C1 coding process is being conducted in regard to the input data related to the C1 code.
Here, what is referred to as the decoding calculations input parameters, basically, is the syndrome (S) and the position (I).
The syndrome (S) is calculated by means of combining the input parameter calculator 9 and the register B.sub.OUT 10 shown in FIG. 3.
FIG. 5 is a construction diagram of the input parameter calculator 9 and the register B.sub.OUT 10.
As is shown in FIG. 5, the input parameter calculator 9 is equipped with the multipliers 24 to 27, the adders 20 to 23, the flag detector 28, and the distributor 29.
Also, the register B.sub.OUT 10 is equipped with the registers 30 to 33 and the registers 34 to 37.
As for the multipliers 24 to 27, the multiplier coefficients are the multipliers for a Galois field of fixed values, and conduct the multiplications of X.alpha..sup.0, X.alpha..sup.1, X.alpha..sup.2, X.alpha..sup.3, respectively.
The erasure flag detector 28 detects whether or not the erasure flag contained in the input data is a "1."
The distributor 29 outputs and stores the output of the binary counter 11 which operates corresponding to each RS unit position contained in the input data in any of the registers 34 to 37 of the register B.sub.OUT 10.
The storage results of these registers 34 to 37 show the erasure positions (I).
The erasure positions (I) are converted to the expression of the Galois field, in other words, from "i" to ".alpha..sup.i ", by means of a later presented converter, at the decoding calculator 17 shown in FIG. 3.
Specifically, I={i.sub.1, i.sub.2, i.sub.3, i.sub.4 } is converted to X={x.sub.1, x.sub.2, x.sub.3, x.sub.4 }.
The decoding calculations corresponding to the above-mentioned Formulas 3, 4, 6, 7, 10 in the case of executing the quadruple erasure error corrections are conducted at the decoding calculations processing section 4, and using the decoding calculation input parameters (S={s.sub.0, s.sub.1, s.sub.2, s.sub.3 } from the register B.sub.OUT 10, and the X={x.sub.1, x.sub.2, x.sub.3, x.sub.4 } that was obtained by converting the I={i.sub.1, i.sub.2, i.sub.3, i.sub.4 }, the decoding calculation output parameters E={e.sub.1, e.sub.2, e.sub.3, e.sub.4 } and X'=X={x.sub.1, x.sub.2, x.sub.3, x.sub.4 } are obtained. In the event the erasure error correction is not conducted, in the above-mentioned double error correction, by using the decoding calculation input parameters (S={s.sub.0, s.sub.1, s.sub.2, s.sub.3 } , the decoding calculation output parameters E={e.sub.1, e.sub.2 } and X'={x'.sub.1, x'.sub.2 } are obtained.
The error positions X for X' are converted to exponential values, in other words, from .alpha..sup.i to i in the later explained converter in the decoding calculation processing section 4. Specifically, X'=X={x.sub.1, x.sub.2, x.sub.3, x.sub.4 } is converted to I={i.sub.1, i.sub.2, i.sub.3, i.sub.4 }, and X'={x'.sub.1, x'.sub.2 } is converted to I'={i'.sub.1, i'.sub.2 }.
FIG. 6 is a construction diagram of the corrections operation implementer 12 and the register B.sub.IN 13.
As is shown in FIG. 6, the corrections operations implementer 12 is equipped with the comparator 40, the adder 45, and the logic gate 46.
Also, the register B.sub.IN 13 is equipped with the registers 41 to 44 and the registers 47 to 50.
The bus I/F block 3 executes the correction operations by using the error value (E) and the error positions (I') that are inputted from the register G.sub.OUT 16.
The binary counter 11 operates in correspondence with the switching of the output from the cache memories 5, 6 by means of the switches 7, 8, and when the binary count value of the binary counter 11 matches any one of the (i'.sub.n) construction elements for the error position (I'), a corresponding error value e.sub.n is output to the adder 45 from the logic gate 46. Also, in the adder 45, the Galois field calculations are conducted in regard to the error value e.sub.n and the data output of the memory block from the switch 8, and the addition results become the output data.
Next, an explanation is given in regard to the decoding calculations processing section 4.
FIG. 7 is a construction diagram of the decoding calculations processing section 4.
As is shown in FIG. 7, the decoding calculations processing section 4 is equipped with the microcode ROM 50, the register 51, the destination controller 52, the working register 53, the GLU (Global Logic Unit) 54, and the port selector 55.
As in the CIRC code, t is less than 4, and in the event the solution is found directly from the simultaneous Formula, and when the processing speed can be comparatively slow, a RISC (Reduced Instruction Set Computer) type of device can be used as the decoding calculations processing section 4.
In the decoding calculations processing section 4, each calculation is conducted sequentially, and the calculations sets are time shared by GLU 54. Also, a series of calculation processes are microcoded, are stored in the microcode ROM 50 as instruction codes, and the process routine (routine for readout from the memory) is controlled by means of the ROM address from the sequencer 51.
Also, during the operations the calculation results are temporarily stored in the multiple working registers 53 that were initialized beforehand, but as to which working register 53 to store in, this is recorded in the destination control code within the instruction code.
According to this method, the process speed is limited, but along with being able to downsize the device due to the time sharing by the GLU 54, the freedom of design can be increased due to the micro-encoding of the calculation processes.
For example, the addition of two elements of the Galois field is equivalent to each bit of an exclusive OR logic operation, and can be realized in one step in the decoding calculations processing section 4. In other words, the GLU 54 includes the function of an exclusive OR logic operation for each bit. However, multiplication in a Galois field is far more complicated compared to addition, and if an attempt is made to realize this by using ROM, it comes to obtain one byte of output for an address input of two bytes, and the scale becomes extremely large.
An explanation is given in regard to the construction of the GLU 54.
FIG. 8 is a construction diagram of the GLU 54.
As is shown in FIG. 8, the GLU 54 is equipped with the logic operation 60, 61, the converters 62, 63, and the operation selector 64.
In the GLU 54, the respective elements of the Galois field for the two input data (a, b) are converted to the values for the exponents for the corresponding original elements, in other words, .alpha..sup.i is converted to i by the converter 62, and additions between the same exponents are executed. Then, the obtained addition results are converted to the element for the corresponding Galois field by the converter 63, in other words, i is converted to .alpha..sup.i .
For example, the multiplication of .alpha..sup.v and .alpha..sup.w is executed, and in obtaining .alpha..sup.v+w, the four calculations shown in the following Formula 11 are necessary, and at least four steps are required in the GLU 54. ##EQU8##
Division is also tone in the same manner, and subtraction is executed in place of the addition in the multiplication.
Therefore, in the above-mentioned method, in the finding of the error values e.sub.1 to e.sub.4, since the multiplication.apprxeq.division in the above-mentioned Formulas 3, 4, 6, 7, 9, and 10 are done 20 times, even with just this, 80 steps or more become necessary. If the 23 steps of addition are included in this, it becomes a total of more than 103 steps.
This invention was made by reviewing the above-mentioned prior art, and its purpose is to offer a Reed-Solomon decoding method that can effectively prevent erroneous correction.
Also, the objective of this invention is to offer a Reed-Solomon decoding method in which the correction method is clarified in the case of n.ltoreq.2 (=t) in regard to the data words of n units.